Track and hold circuits are used for capturing and holding voltage amplitude values of a continuous time input signal at predetermined times. In a typical application, a track and hold circuit holds voltage values at predetermined times or intervals and an analog-to-digital converter samples the held voltage values at the output of the track and hold circuit and converts the held values into digital signals. Conceptually, a track and hold circuit includes a switch and an amplitude storage device. In the track mode, the switch is closed thereby coupling the input signal to the storage device, and thereby allowing the amplitude storage device to follow or track the input signal. In the hold mode, the switch is open, which isolates the storage device from the input signal, and allows the storage device to hold constant the amplitude value of the input signal at the time the switch was opened.
FIG. 1 is schematic illustration of a known track and hold circuit 5. The track and hold circuit 5 includes an electronic switch 10, a hold capacitor 20, which functions as the amplitude storage device, and a buffer amplifier 30. In the track and hold circuit 5, it is the voltage amplitude of the input signal 40 that is tracked and held. A HOLD signal 50 controls the electronic switch 10. The HOLD signal 50 opens the electronic switch 10, placing the track and hold circuit 5 in a hold mode, in which the voltage of the input signal 40 at the time the electronic switch 10 opened is held by the hold capacitor 20. The HOLD signal 50 is also used to close the electronic switch 10, placing the track and hold circuit 5 in a track mode, in which the voltage on the hold capacitor 20 continuously tracks the voltage of the input signal 40. The buffer amplifier 30 prevents external circuitry that may be coupled to the output 60 of the track and hold circuit 5 from discharging the hold capacitor 20.
The rate at which the track and hold circuit 5 is alternated between the track and hold modes is called the sample rate. A time required to charge the hold capacitor 20 to the voltage of the input signal 40 during the track mode places a limit on the maximum sample rate of the track and hold circuit 5. Reducing the time required to charge the hold capacitor 20 increases the sample rate limit. The time required to charge the hold capacitor 20 may be reduced by decreasing the capacitance value of the hold capacitor 20 and/or by decreasing the residual resistance (ON resistance) of the electronic switch 10 (e.g., by using a lower ON resistance switch for the electronic switch 10. Other constraints imposed by the implementation technology used for the components of the track and hold circuit 5 place lower bounds on the values of the capacitance of the hold capacitor 20 and the ON resistance of the electronic switch 10.
Presently, silicon-based complementary metal-oxide-semiconductor (CMOS) technology is the least costly integrated circuit technology. When the required sample rate of the track and hold circuit exceeds somewhere about 2 gigahertz (GHz) to 5 GHz, imperfections in CMOS technology has limited its application. One way around the sample rate limitation of CMOS has been to employ a faster integrated circuit technology, for example, using technologies such as gallium arsenide (GaAs), silicon-germanium (SiGe), and indium phosphide/gallium arsenide (InP/GaAs). Work in this area has yielded faster track and hold circuits, but circuits fabricated using these technologies come at a higher cost.
FIG. 2 is a schematic diagram of a known track and hold circuit 100, which is referred to as a single-ended common-drain based track and hold circuit. In the circuit 100, an input signal is coupled to a source follower circuit including an n-type metal oxide semiconductor (NMOS) input device 102 and an NMOS bias device 104. A supply voltage (Vsupply) is coupled to the NMOS input device 102 and a bias signal is provided to a gate of the NMOS bias device 104.
In operation, the source follower formed by the devices 102 and 104 steps down the voltage provided at the gate of the NMOS input device 102 and provides the stepped-down voltage to an NMOS switching device 106, the output of which is coupled to an NMOS dummy switch 108, which provides charge cancellation functionality. The signals designated as hold bar and hold that are provided to the gates of the devices 106 and 108 control whether the stepped-down voltage provided by the source follower of devices 102 and 104 is tracked or held. When the stepped-down voltage is not held, the hold bar and hold signals control the devices 106 and 108 to pass the stepped-down voltage to a gate of a p-type metal oxide semiconductor (PMOS) output device 110. The PMOS output device 110 operates in conjunction with a PMOS bias device 112 to amplify the stepped-down voltage provided from the device 108 back to the level of the original input signal provided at the gate of the NMOS input device 102.
In contrast, when the stepped-down voltage is to be held, the hold bar and hold signals control the devices 106 and 108 to disconnect the stepped-down voltage from the gate of the device 110. When the stepped down voltage from the gate of the device 110 is disconnected from the device 110, the device 110 holds the prior value that it received, owning to capacitance of the device 110. Accordingly, it is that prior, or held, value of the stepped-down voltage that is stepped up and output.
As will be readily appreciated by those having ordinary skill in the art, the circuit of FIG. 2 is a single-ended circuit. For the purpose of eliminating common mode noise, differential circuits are commonly used, wherein an input signal and its complement are each coupled to a separate branch of a circuit and, therefore, noise common to both branches of the circuit may be eliminated. It is known to use two separate instances of the circuit in FIG. 2 to construct a pseudo-differential circuit. However, because the two circuits are physically separate, there is a reduction in the amount of common mode noise that is eliminated through a pseudo-differential circuit.
Wherever possible, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or similar parts.